`timescale 1ns / 1ps
`include "defines.vh"

//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/10 11:28:00
// Design Name: 
// Module Name: PC
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


//计数并输出指令地址
module PC(
    input [0:0] rst,
    input [0:0] clk,
    output [`Instruction_Bus] addr_Output,

    //跳转标志位及其地址
    input [0:0] jump_flag_Input,
    input [`Instruction_Addr_Bus] jump_addr_Input,

    //暂停标志位
    input [0:0] Hold_flag_Input
    );

    reg [`Instruction_Addr_Bus] addr_reg = `PC_Addr_Rst;


    always @(posedge clk)begin
        // 复位
        if( rst == `Rst_Enabled)  begin
            addr_reg <= `PC_Addr_Rst;
        end 
        // 跳转
        else if(jump_flag_Input == `Jump_Flag_Enabled) begin
            addr_reg <= jump_addr_Input;
        end
        // 停止
        else if(Hold_flag_Input == `Hold_Flag_Enabled) begin
            addr_reg <= addr_reg;
        end
        // 继续下一条
        else begin
            addr_reg <= addr_reg + `Instruction_Length;
        end

        $display($time,"  PC:  In => rst: %d, jump_flag: %d, jump_addr: %d,Hold_flag: %d       Out => Address: %d",rst,jump_flag_Input,jump_addr_Input,Hold_flag_Input,addr_Output);
    end

    assign addr_Output = addr_reg;



endmodule
